august 2009 ?2009 fairchild semiconductor corporation FDMS7650 rev . e www.fairchildsemi.com 1 FDMS7650 n-channel powertrench ? mosfet FDMS7650 n-channel powertrench ? mosfet 30 v, 60 a, 0.99 m ? features ? max r ds(on) = 0.99 m ? at v gs = 10 v, i d = 36 a ? max r ds(on) = 1.55 m ? at v gs = 4.5 v, i d = 32 a ? advanced package and silic on combination for low r ds(on) and high efficiency ? msl1 robust package design ? 100% uil tested ? rohs compliant general description this n-channel mosfet has been designed specifically to improve the overall efficien cy and to minimize switch node ringing of dc/dc converters using either synchronous or conventional switching pwm c ontrollers. it has been optimized for low gate charge and extremely low r ds(on) . applications ? oringfet ? synchronous rectifier bottom top pin 1 s g s s d d d d g s s s d d d d 5 6 7 8 3 2 1 4 power 56 mosfet maximum ratings t c = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage (note 4) 20 v i d drain current -continuous (package limited) t c = 25 c 60 a -continuous (silicon limited) t c = 25 c 232 -continuous t a = 25 c (note 1a) 36 -pulsed 450 e as single pulse avalanche energy (note 3) 544 mj p d power dissipation t c = 25 c 104 w power dissipation t a = 25 c (note 1a) 2.5 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 1.2 c/w r ja thermal resistance, junction to ambient (note 1a) 50 device marking device package reel size tape width quantity FDMS7650 FDMS7650 power 56 13 ?? 12 mm 3000 units
www.fairchildsemi.com 2 ?2009 fairchild semiconductor corporation FDMS7650 rev . e FDMS7650 n-channel powertrench ? mosfet electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 30 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 15 mv / c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a11.93v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -6 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 36 a 0.8 0.99 m ? v gs = 4.5 v, i d = 32 a 1.1 1.55 v gs = 10 v, i d = 36 a, t j = 125 c 1.1 1.7 g fs forward transconductance v ds = 5 v, i d = 36 a 267 s c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1 mhz 11250 14965 pf c oss output capacitance 3050 4055 pf c rss reverse transfer capacitance 240 360 pf r g gate resistance 1.4 3 ? t d(on) turn-on delay time v dd = 15 v, i d = 36 a, v gs = 10 v, r gen = 6 ? 28 45 ns t r rise time 24 38 ns t d(off) turn-off delay time 83 133 ns t f fall time 21 34 ns q g total gate charge v gs = 0 v to 10 v v dd = 15 v, i d = 36 a 149 209 nc q g total gate charge v gs = 0 v to 4.5 v 63 88 nc q gs gate to source charge 34 nc q gd gate to drain ?miller? charge 13 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 2.1 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 36 a (note 2) 0.8 1.3 t rr reverse recovery time i f = 36 a, di/dt = 100 a/ s 69 97 ns q rr reverse recovery charge 56 90 nc notes : 1. r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25 c, l = 1 mh, i as = 33 a, v dd = 27 v, v gs = 10 v. 4. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied. a. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 125 c/w when mounted on a minimum pad of 2 oz copper.
www.fairchildsemi.com 3 ?2009 fairchild semiconductor corporation FDMS7650 rev e FDMS7650 n-channel powertrench ? mosfet typical characteristics t j = 25 c unless otherwise noted figure 1. 0 0.5 1.0 1.5 2.0 0 40 80 120 160 200 v gs = 4.5 v v gs = 10 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 3 v v gs = 3.5 v v gs = 4 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 40 80 120 160 200 0 1 2 3 4 5 6 7 v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 10 v v gs = 3 v v gs = 4 v v gs = 3.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.8 1.0 1.2 1.4 1.6 i d = 36 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 246810 0 2 4 6 8 10 i d = 36a t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1234 0 40 80 120 160 200 v ds = 3 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c t j = 150 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
www.fairchildsemi.com 4 ?2009 fairchild semiconductor corporation FDMS7650 rev e FDMS7650 n-channel powertrench ? mosfet figure 7. 0 40 80 120 160 0 2 4 6 8 10 q g , gate charge (nc) v gs , gate to source voltage (v) i d = 36 a v dd = 20 v v dd = 10 v v dd = 15 v gate charge characteristics figure 8. 0.1 1 10 30 100 1000 10000 20000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 10 -3 10 -2 10 -1 11010 2 10 3 1 10 t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 100 u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 50 100 150 200 250 limited by package r t jc = 1.2 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e operating area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 1000 dc 100 ms 10 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c figure 12. 10 -3 10 -2 10 -1 110 100 1000 1 10 100 1000 single pulse r t ja = 125 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 5 ?2009 fairchild semiconductor corporation FDMS7650 rev e FDMS7650 n-channel powertrench ? mosfet figure 13. junction-to-ambient transient thermal response curve 10 -3 10 -2 10 -1 110 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
www.fairchildsemi.com 6 ?2009 fairchild semiconductor corporation FDMS7650 rev . e FDMS7650 n-channel powertrench ? mosfet dimensional outlin e and pad layout
FDMS7650 n-channel powertrench ? mosfet ?2009 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMS7650 rev . e trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life su pport device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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